1.For how many of its 4 input rows is a NAND gate's output 0?

2.¬(a ∧ b) equals:

3.A minterm is read from a truth-table row where the output is:

4.In a 4-variable K-map, a group of 8 cells yields a term with how many literals?

5.Which set is NOT functionally complete?

6.Two-level AND-OR logic is equivalent to:

7.Why are K-map axes labelled 00,01,11,10?

8.A 2-input multiplexer computes:

1.Converting decimal to base b, you read the remainders:

2.The 4-bit 2's-complement of 0011 (3) is:

3.Range of an 8-bit 2's-complement number:

4.Adding two negative numbers gives a positive result. This means:

5.Which flag indicates UNSIGNED overflow?

6.A full adder's sum output is:

7.Sign-extending −4 (1100) to 8 bits gives:

8.A single parity bit can:

1.The forbidden input of an SR latch is:

2.A transparent D-latch passes D to Q:

3.Setup time is the interval D must be stable:

4.Max clock frequency is bounded by:

5.On a shared bus, how many output enables may be active at once?

6.The 'Z' state of a 3-state output means:

7.A 2→4 decoder plus 3-state buffers builds a:

8.A JK flip-flop toggles when:

1.A Moore machine's output depends on:

2.Which machine usually needs fewer states?

3.Two states may be merged if they have the same output and:

4.One-hot encoding for 5 states uses how many flip-flops?

5.Gray-coding cyclic states helps because:

6.Synchronous circuits tolerate combinational glitches because:

7.In the FSM design flow, Karnaugh maps are used to:

1.The von Neumann architecture stores:

2.Which is an IMPLEMENTATION-only register?

3.Instruction fetch takes how many cycles (no prefetch)?

4.'LOAD R3 [R1]' uses which addressing?

5.A STOR instruction's destination operand must be:

6.The Conductor is:

7.With prefetch, 'ADD RA RB' drops from 4 cycles to:

8.When polling input, the carry flag C=1 means:

1.Pushing onto the stack:

2.Return addresses are kept on a stack to allow:

3.RTI differs from RTS in that it also restores:

4.On ARM, which register is the link register?

5.ARM 'ADDEQ R1,R1,#1' executes:

6.On ARM, 'MOV R0,R1,LSL #2' computes:

7.To load an arbitrary 32-bit constant on ARM you use:

8.After 'SUB SP locals', a parameter previously at SP+1 is now at:

1.A compiler differs from an interpreter in that it:

2.BNF is used to describe a language's:

3.In the translation convention, an expression's result is left:

4.A 20-bit address bus can address:

5.DRAM differs from SRAM in that it:

6.Caches were introduced because:

7.Out-of-order execution preserves:

8.An atomic synchronisation instruction is:

1.A context switch is usually triggered by:

2.Semaphores are needed because operations like x:=x+1 are:

3.The page table maps:

4.On a page fault, after swapping in the page the CPU:

5.The executable bit on a page controls whether the page may be:

6.The optimal page-replacement policy is not implementable because it:

7.Segmentation (vs paging) primarily provides: