45 key terms

Combinational circuit

A circuit whose output depends only on current inputs; no feedback/cycles.

Sequential circuit

A circuit with memory; output depends on inputs and past state.

Minterm / Maxterm

Product term for a 1-row / sum term for a 0-row of a truth table.

DNF / CNF

Disjunctive (OR of minterms) / Conjunctive (AND of maxterms) normal form.

Karnaugh map

Gray-coded grid for visual two-level minimisation by grouping adjacent cells.

Functional completeness

A gate set that can realise every Boolean function (e.g. {NAND}).

Multiplexer (MUX)

Selects one of several inputs via select lines; a universal function block.

Two's complement

Signed representation where the MSB has weight −2^{n-1}; negate by invert+1.

Overflow (V)

Result not representable; for add, operands same sign but result differs / carry_n≠carry_{n-1}.

Condition codes (C,N,V,Z)

Flags set by the ALU: carry, negative, overflow, zero.

Latch

Level-sensitive storage element; transparent while enabled.

Flip-flop

Edge-triggered storage element; samples input at the clock edge.

Metastability

Unstable, unpredictable output when timing constraints are violated.

Setup / Hold time

Interval the input must be stable before / after the clock edge.

Register

A bank of flip-flops sharing a clock and enable, storing a word.

3-state output

Output that can be 0, 1, or high-impedance Z (disconnected).

Decoder

Converts an n-bit address into one of 2^n one-hot outputs.

Finite state machine

States + guarded transitions + outputs; specifies circuits with memory.

Moore / Mealy machine

Output depends on state only / on state and input.

One-hot encoding

State assignment with one flip-flop (and one '1') per state.

von Neumann architecture

Stored-program computer: code and data share one memory.

ALU

Arithmetic-logic unit; performs add/sub/logic and produces condition codes.

Register Transfer Language (RTL)

Notation 'dest ← expr' describing per-cycle datapath transfers.

The Conductor

The control FSM sequencing the datapath to execute instructions.

Addressing mode

How an operand's location is specified (immediate, direct, indirect, indexed…).

Prefetching

Fetching the next instruction while finishing the current one.

Stack / Stack pointer

LIFO memory region; SP marks the top, grows downward.

Subroutine

Reusable code called from many places; return address kept on the stack.

Interrupt

External event that diverts the CPU to a handler; RTI resumes (restoring flags).

RISC / CISC

Reduced (simple, fixed instructions, e.g. ARM) / Complex (rich, variable, e.g. x86).

Barrel shifter

ARM shifter before the ALU enabling free shifts on an operand.

Link register (LR)

ARM register holding the subroutine return address (set by BL).

Software interrupt (SWI/TRAP)

Instruction that calls a supervisor routine (system call).

Compiler / Interpreter

Translates a program to machine code / executes it directly.

Context-free grammar (BNF)

Rules defining a language's syntax; drives parsing into a parse tree.

Cache

Small fast memory holding copies of recently used data near the core.

Cache coherency

Keeping shared data consistent across multiple cores' caches.

Out-of-order execution

Running instructions as data is ready, respecting only true dependencies.

Semaphore / Mutex

Synchronisation primitive (Dijkstra P/V) enforcing mutual exclusion.

Context switch

Saving one process's state and restoring another's to share the CPU.

Virtual memory

Address space larger than RAM, backed by disc via paging.

Paging / Page table / MMU

Fixed-size memory blocks / virtual→physical map / hardware that translates.

Page fault

Trap when a referenced page is absent; handler swaps it in and retries.

Segmentation

Multiple independent, growable address spaces (segment number + offset).

LRU / FIFO replacement

Evict the least-recently-used / oldest-loaded page.

Match the definitions