Assembly lab

PP2 and ARM instruction summaries, addressing modes, and code patterns.

PP2 and ARM reference

The PP2 simulator executes every mnemonic in the PP2 tab. ARM uses registers R0–R15 with aliases SB=R9, IP=R12, SP=R13, LR=R14, PC=R15.

Instructions

Instruction	Effect	Example
$LOAD Ri, operand$	$Ri \leftarrow operand (sets Z,N)$	$LOAD R0, [R1] \cdot LOAD R1, 42$
$STOR Ri, operand$	$operand \leftarrow Ri (sets Z,N)$	$STOR R0, [R2] \cdot STOR R1, [--SP]$
$ADD Ri, operand$	$Ri \leftarrow Ri + operand (Z,N,C,V)$	$ADD R0, R1 \cdot ADD R2, [R3]$
$SUB Ri, operand$	$Ri \leftarrow Ri - operand (Z,N,C,V)$	$SUB R0, R1$
$CMP Ri, operand$	$Compute Ri - operand, set CC (no write)$	$CMP R0, 0$
$MUL Ri, operand$	$Ri \leftarrow Ri \times operand (Z,N,C,V)$	$MUL R0, R1$
$DIV Ri, operand$	$Ri \leftarrow Ri \div operand (Z,N,C,V)$	$DIV R0, R1$
$MOD Ri, operand$	$Ri \leftarrow Ri mod operand (Z,N,C,V)$	$MOD R0, R1$
$AND Ri, operand$	$Ri \leftarrow Ri \land operand (Z,N)$	$AND R0, R1$
$OR Ri, operand$	$Ri \leftarrow Ri \lor operand (Z,N)$	$OR R0, 1$
$XOR Ri, operand$	$Ri \leftarrow Ri \oplus operand (Z,N)$	$XOR R0, R0 ; clear$
$BRA disp$	$IP \leftarrow IP + disp (unconditional)$	$BRA loop$
$BRS Ri disp$	$RAM[Ri-1]\leftarrowIP; IP\leftarrowIP+disp; Ri\leftarrowRi-1 (call)$	$BRS R7, sub$
$RTS Ri$	$IP \leftarrow RAM[Ri]; Ri \leftarrow Ri+1 (return)$	$RTS R7$
$BEQ disp$	$Branch if Z=1 (equal)$	$BEQ done$
$BNE disp$	$Branch if Z=0 (not equal)$	$BNE again$
$BCS disp$	$Branch if C=1 (carry set)$	$BCS ovf$
$BCC disp$	$Branch if C=0 (carry clear)$	$BCC ok$
$BLS disp$	$Branch if Z=1 \lor C=1 (unsigned \leq)$	$BLS le$
$BHI disp$	$Branch if Z=0 \land C=0 (unsigned >)$	$BHI gt$
$BVC disp$	$Branch if V=0 (no overflow)$	$BVC ok$
$BVS disp$	$Branch if V=1 (overflow)$	$BVS ovf$
$BPL disp$	$Branch if N=0 (\geq 0)$	$BPL pos$
$BMI disp$	$Branch if N=1 (< 0)$	$BMI neg$
$BLT disp$	$Branch if N\neqV (signed <)$	$BLT lt$
$BGE disp$	$Branch if N=V (signed \geq)$	$BGE ge$
$BLE disp$	$Branch if N\neqV \lor Z=1 (signed \leq)$	$BLE end$
$BGT disp$	$Branch if N=V \land Z=0 (signed >)$	$BGT pos$
$PUSH Ri$	$= STOR Ri, [--SP]$	$PUSH R0$
$PULL Ri$	$= LOAD Ri, [SP++]$	$PULL R0$

Addressing modes

Operand	Addressing mode	Example
$val$	$Immediate value$	$ADD R0, 5 \to R0+5$
$Ri$	$Register$	$ADD R0, R1 \to R0 = R0+R1$
$[Ri]$	$Indirect (register)$	$LOAD R0, [R1] \to R0 = RAM[R1]$
$[Ri-val]$	$Register indexed$	$LOAD R0, [R1-2] \to R0 = RAM[R1-2]$
$[Ri\cdotRj]$	$Register-register indexed$	$LOAD R0, [R1+R2] \to R0 = RAM[R1+R2]$
$[Ri++]$	$Register, post-increment$	$LOAD R0, [R1++] \to R0=RAM[R1]; R1++$
$[--Ri]$	$Register, pre-decrement$	$STOR R0, [--R1] \to R1--; RAM[R1]=R0$
$[[Ri]]$	$Double indirect$	$LOAD R0, [[R1]] \to R0 = RAM[RAM[R1]]$
$[val]$	$Indirect (absolute address)$	$LOAD R0, [100] \to R0 = RAM[100]$

2IC30 · resource

Assembly lab

PP2 and ARM instruction summaries, addressing modes, and code patterns.

PP2 and ARM reference

The PP2 simulator executes every mnemonic in the PP2 tab. ARM uses registers R0–R15 with aliases SB=R9, IP=R12, SP=R13, LR=R14, PC=R15.

Instructions

Instruction	Effect	Example
$LOAD Ri, operand$	$Ri \leftarrow operand (sets Z,N)$	$LOAD R0, [R1] \cdot LOAD R1, 42$
$STOR Ri, operand$	$operand \leftarrow Ri (sets Z,N)$	$STOR R0, [R2] \cdot STOR R1, [--SP]$
$ADD Ri, operand$	$Ri \leftarrow Ri + operand (Z,N,C,V)$	$ADD R0, R1 \cdot ADD R2, [R3]$
$SUB Ri, operand$	$Ri \leftarrow Ri - operand (Z,N,C,V)$	$SUB R0, R1$
$CMP Ri, operand$	$Compute Ri - operand, set CC (no write)$	$CMP R0, 0$
$MUL Ri, operand$	$Ri \leftarrow Ri \times operand (Z,N,C,V)$	$MUL R0, R1$
$DIV Ri, operand$	$Ri \leftarrow Ri \div operand (Z,N,C,V)$	$DIV R0, R1$
$MOD Ri, operand$	$Ri \leftarrow Ri mod operand (Z,N,C,V)$	$MOD R0, R1$
$AND Ri, operand$	$Ri \leftarrow Ri \land operand (Z,N)$	$AND R0, R1$
$OR Ri, operand$	$Ri \leftarrow Ri \lor operand (Z,N)$	$OR R0, 1$
$XOR Ri, operand$	$Ri \leftarrow Ri \oplus operand (Z,N)$	$XOR R0, R0 ; clear$
$BRA disp$	$IP \leftarrow IP + disp (unconditional)$	$BRA loop$
$BRS Ri disp$	$RAM[Ri-1]\leftarrowIP; IP\leftarrowIP+disp; Ri\leftarrowRi-1 (call)$	$BRS R7, sub$
$RTS Ri$	$IP \leftarrow RAM[Ri]; Ri \leftarrow Ri+1 (return)$	$RTS R7$
$BEQ disp$	$Branch if Z=1 (equal)$	$BEQ done$
$BNE disp$	$Branch if Z=0 (not equal)$	$BNE again$
$BCS disp$	$Branch if C=1 (carry set)$	$BCS ovf$
$BCC disp$	$Branch if C=0 (carry clear)$	$BCC ok$
$BLS disp$	$Branch if Z=1 \lor C=1 (unsigned \leq)$	$BLS le$
$BHI disp$	$Branch if Z=0 \land C=0 (unsigned >)$	$BHI gt$
$BVC disp$	$Branch if V=0 (no overflow)$	$BVC ok$
$BVS disp$	$Branch if V=1 (overflow)$	$BVS ovf$
$BPL disp$	$Branch if N=0 (\geq 0)$	$BPL pos$
$BMI disp$	$Branch if N=1 (< 0)$	$BMI neg$
$BLT disp$	$Branch if N\neqV (signed <)$	$BLT lt$
$BGE disp$	$Branch if N=V (signed \geq)$	$BGE ge$
$BLE disp$	$Branch if N\neqV \lor Z=1 (signed \leq)$	$BLE end$
$BGT disp$	$Branch if N=V \land Z=0 (signed >)$	$BGT pos$
$PUSH Ri$	$= STOR Ri, [--SP]$	$PUSH R0$
$PULL Ri$	$= LOAD Ri, [SP++]$	$PULL R0$

Addressing modes

Operand	Addressing mode	Example
$val$	$Immediate value$	$ADD R0, 5 \to R0+5$
$Ri$	$Register$	$ADD R0, R1 \to R0 = R0+R1$
$[Ri]$	$Indirect (register)$	$LOAD R0, [R1] \to R0 = RAM[R1]$
$[Ri-val]$	$Register indexed$	$LOAD R0, [R1-2] \to R0 = RAM[R1-2]$
$[Ri\cdotRj]$	$Register-register indexed$	$LOAD R0, [R1+R2] \to R0 = RAM[R1+R2]$
$[Ri++]$	$Register, post-increment$	$LOAD R0, [R1++] \to R0=RAM[R1]; R1++$
$[--Ri]$	$Register, pre-decrement$	$STOR R0, [--R1] \to R1--; RAM[R1]=R0$
$[[Ri]]$	$Double indirect$	$LOAD R0, [[R1]] \to R0 = RAM[RAM[R1]]$
$[val]$	$Indirect (absolute address)$	$LOAD R0, [100] \to R0 = RAM[100]$

2IC30 · resource

Assembly lab

PP2 and ARM instruction summaries, addressing modes, and code patterns.

PP2 and ARM reference

The PP2 simulator executes every mnemonic in the PP2 tab. ARM uses registers R0–R15 with aliases SB=R9, IP=R12, SP=R13, LR=R14, PC=R15.

Instructions

Instruction	Effect	Example
$LOAD Ri, operand$	$Ri \leftarrow operand (sets Z,N)$	$LOAD R0, [R1] \cdot LOAD R1, 42$
$STOR Ri, operand$	$operand \leftarrow Ri (sets Z,N)$	$STOR R0, [R2] \cdot STOR R1, [--SP]$
$ADD Ri, operand$	$Ri \leftarrow Ri + operand (Z,N,C,V)$	$ADD R0, R1 \cdot ADD R2, [R3]$
$SUB Ri, operand$	$Ri \leftarrow Ri - operand (Z,N,C,V)$	$SUB R0, R1$
$CMP Ri, operand$	$Compute Ri - operand, set CC (no write)$	$CMP R0, 0$
$MUL Ri, operand$	$Ri \leftarrow Ri \times operand (Z,N,C,V)$	$MUL R0, R1$
$DIV Ri, operand$	$Ri \leftarrow Ri \div operand (Z,N,C,V)$	$DIV R0, R1$
$MOD Ri, operand$	$Ri \leftarrow Ri mod operand (Z,N,C,V)$	$MOD R0, R1$
$AND Ri, operand$	$Ri \leftarrow Ri \land operand (Z,N)$	$AND R0, R1$
$OR Ri, operand$	$Ri \leftarrow Ri \lor operand (Z,N)$	$OR R0, 1$
$XOR Ri, operand$	$Ri \leftarrow Ri \oplus operand (Z,N)$	$XOR R0, R0 ; clear$
$BRA disp$	$IP \leftarrow IP + disp (unconditional)$	$BRA loop$
$BRS Ri disp$	$RAM[Ri-1]\leftarrowIP; IP\leftarrowIP+disp; Ri\leftarrowRi-1 (call)$	$BRS R7, sub$
$RTS Ri$	$IP \leftarrow RAM[Ri]; Ri \leftarrow Ri+1 (return)$	$RTS R7$
$BEQ disp$	$Branch if Z=1 (equal)$	$BEQ done$
$BNE disp$	$Branch if Z=0 (not equal)$	$BNE again$
$BCS disp$	$Branch if C=1 (carry set)$	$BCS ovf$
$BCC disp$	$Branch if C=0 (carry clear)$	$BCC ok$
$BLS disp$	$Branch if Z=1 \lor C=1 (unsigned \leq)$	$BLS le$
$BHI disp$	$Branch if Z=0 \land C=0 (unsigned >)$	$BHI gt$
$BVC disp$	$Branch if V=0 (no overflow)$	$BVC ok$
$BVS disp$	$Branch if V=1 (overflow)$	$BVS ovf$
$BPL disp$	$Branch if N=0 (\geq 0)$	$BPL pos$
$BMI disp$	$Branch if N=1 (< 0)$	$BMI neg$
$BLT disp$	$Branch if N\neqV (signed <)$	$BLT lt$
$BGE disp$	$Branch if N=V (signed \geq)$	$BGE ge$
$BLE disp$	$Branch if N\neqV \lor Z=1 (signed \leq)$	$BLE end$
$BGT disp$	$Branch if N=V \land Z=0 (signed >)$	$BGT pos$
$PUSH Ri$	$= STOR Ri, [--SP]$	$PUSH R0$
$PULL Ri$	$= LOAD Ri, [SP++]$	$PULL R0$

Addressing modes

Operand	Addressing mode	Example
$val$	$Immediate value$	$ADD R0, 5 \to R0+5$
$Ri$	$Register$	$ADD R0, R1 \to R0 = R0+R1$
$[Ri]$	$Indirect (register)$	$LOAD R0, [R1] \to R0 = RAM[R1]$
$[Ri-val]$	$Register indexed$	$LOAD R0, [R1-2] \to R0 = RAM[R1-2]$
$[Ri\cdotRj]$	$Register-register indexed$	$LOAD R0, [R1+R2] \to R0 = RAM[R1+R2]$
$[Ri++]$	$Register, post-increment$	$LOAD R0, [R1++] \to R0=RAM[R1]; R1++$
$[--Ri]$	$Register, pre-decrement$	$STOR R0, [--R1] \to R1--; RAM[R1]=R0$
$[[Ri]]$	$Double indirect$	$LOAD R0, [[R1]] \to R0 = RAM[RAM[R1]]$
$[val]$	$Indirect (absolute address)$	$LOAD R0, [100] \to R0 = RAM[100]$