2IC30Computer Systems

2IC30 · resource

RTL crashcourse

The fixed recipe that produces a full-marks Q4 answer.

Q4 = ~16 pts. It is the most mechanical question on the exam: there is a fixed recipe that produces a full-marks answer every time. Learn the recipe, the atoms, and the checklist below — then drill in the RTL Lab.

Registers

IP instruction pointer · R0–R3 general · CC flags (visible)
IR instruction reg · ΣA RAM address · ΣR RAM read · ΣW RAM write (internal)

Three buses

Abus → ALU input A (IP, RA, ΣA)
Bbus → ALU input B (IP, IR, ΣR, RB via RAB)
Cbus → ALU result back to a register

0 · The machine you write for

ALU ops you name each cycle: incA (A+1), decA (A−1), loadA/loadB (pass through), add, sub, and, or, xor.

1 · ALWAYS start with the 3-cycle fetch

Memorise this verbatim. Every instruction begins with it. Writing it wins free points and never changes:

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) ; address = IP, then IP++ 1: ΣR ← RAM[ΣA] ; read the instruction word 2: IR ← ΣR(Bbus) (loadB) ; decode it ⚠ Skip the fetch = lose marks on every single Q4. Never skip it.

2 · The universal recipe

Write the 3 fetch cycles (cycles 0–2).
Fetch each operand — one dereference per [ ] level (see atoms below).
Execute — do the ALU op, write the result, set CC if the instruction sets flags.
Annotate every cycle: which bus carries each value + which ALU op (or "none").
Number cycles from 0.

3 · The atoms (reusable building blocks)

Every Q4 answer is these glued together. Learn the 5 atoms:

Atom	RTL	Notes
Read memory	ΣA ← addr · ΣR ← RAM[ΣA]	2 cycles. addr can be RB, IP, ΣR…
Write memory	ΣA, ΣW ← addr, data · RAM[ΣA] ← ΣW	load address + data, then store. No Cbus (it is a write).
Dereference [x]	ΣA ← x ; ΣR ← RAM[ΣA]	One per bracket level. [[x]] = do it twice.
ALU on two regs	RA, CC ← RA(Abus) op RB(Bbus)	1 cycle. Result on Cbus → RA. Set CC if flagged.
Branch displacement	IP ← IP(Abus)+IR.compl(Bbus) (add)	Sign-extended displacement from IR added to IP.

cycles = 3 (fetch) + 2 × (number of [ ] indirection levels) + 1 (execute)

Instruction	Levels	Cycles
ADD RA RB	0	3+0+1 = 4
ADD RA [RB]	1	3+2+1 = 6
LOAD RA [[RB]]	2	3+4+1 = 8
STOR RA [RB]	1 (write)	3+1+1 = 5

4 · Cycle-count formula (sanity check)

If your cycle count does not match this, you missed or doubled a step. Recount.

A · ADD RA RB (0 levels → 4 cycles)

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: RA, CC ← RA(Abus) + RB(Bbus) (add) ; execute + flags

B · ADD RA [RB] (1 level → 6 cycles)

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: ΣA ← RB(Bbus) ; dereference: address = RB 4: ΣR ← RAM[ΣA] ; ΣR = RAM[RB] 5: RA, CC ← RA(Abus) + ΣR(Bbus) (add) ; execute + flags

C · LOAD RA [[RB]] (2 levels → 8 cycles)

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: ΣA ← RB(Bbus) ; level 1 4: ΣR ← RAM[ΣA] ; = RAM[RB] 5: ΣA ← ΣR(Bbus) ; level 2 6: ΣR ← RAM[ΣA] ; = RAM[RAM[RB]] 7: RA, CC ← ΣR(Bbus) (loadB) ; load + flags

D · STOR RA [RB] (write → 5 cycles)

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: ΣA, ΣW ← RB(Bbus), RA(Abus) ; address = RB, data = RA 4: RAM[ΣA] ← ΣW ; write. no CC, no Cbus

E · BRS Ri disp (real 2026 Q4a, 10 pts)

Spec: store IP at RAM[ra−1], set Ri=ra−1, then IP += disp. Uses RAB = register on Bbus.

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: RA ← RA(Abus) − 1 (decA) ; Ri = ra−1 4: ΣA, ΣW ← RAB(Bbus), IP(Abus) ; addr = ra−1, data = IP 5: IP, RAM[ΣA] ← IP(Abus)+IR.compl(Bbus), ΣW (add) ; save IP + branch

6 · Point-losers checklist (the stuff graders deduct for)

❌ Skipping the 3-cycle fetch.
❌ Two output-enables on the same bus in one cycle (bus contention) — only ONE driver per bus per cycle.
❌ Forgetting to set CC on ALU/LOAD instructions that require flags.
❌ Not naming the bus or ALU op on a cycle (write them even when "obvious").
❌ Using register names/buses that don't match the figure the exam gives you — copy theirs exactly.
❌ Wrong cycle count — always cross-check with the formula in §4.

7 · Full-marks ritual (do this on every Q4)

Write the 3 fetch cycles first, from memory.
Count the [ ] levels → predict the cycle count with the §4 formula.
Add 2 cycles per level using the read/write atom.
Add the execute cycle; set CC if needed.
Re-read each cycle: one driver per bus? ALU op named? bus named?
Final cycle number + 1 = your predicted count. Match? Done.

7 · Full-marks ritual (do this on every Q4)

Drill it now in the RTL Lab →

2IC30 · resource

RTL crashcourse

The fixed recipe that produces a full-marks Q4 answer.

Registers

IP instruction pointer · R0–R3 general · CC flags (visible)
IR instruction reg · ΣA RAM address · ΣR RAM read · ΣW RAM write (internal)

Three buses

Abus → ALU input A (IP, RA, ΣA)
Bbus → ALU input B (IP, IR, ΣR, RB via RAB)
Cbus → ALU result back to a register

0 · The machine you write for

ALU ops you name each cycle: incA (A+1), decA (A−1), loadA/loadB (pass through), add, sub, and, or, xor.

1 · ALWAYS start with the 3-cycle fetch

Memorise this verbatim. Every instruction begins with it. Writing it wins free points and never changes:

2 · The universal recipe

Write the 3 fetch cycles (cycles 0–2).
Fetch each operand — one dereference per [ ] level (see atoms below).
Execute — do the ALU op, write the result, set CC if the instruction sets flags.
Annotate every cycle: which bus carries each value + which ALU op (or "none").
Number cycles from 0.

3 · The atoms (reusable building blocks)

Every Q4 answer is these glued together. Learn the 5 atoms:

Atom	RTL	Notes
Read memory	ΣA ← addr · ΣR ← RAM[ΣA]	2 cycles. addr can be RB, IP, ΣR…
Write memory	ΣA, ΣW ← addr, data · RAM[ΣA] ← ΣW	load address + data, then store. No Cbus (it is a write).
Dereference [x]	ΣA ← x ; ΣR ← RAM[ΣA]	One per bracket level. [[x]] = do it twice.
ALU on two regs	RA, CC ← RA(Abus) op RB(Bbus)	1 cycle. Result on Cbus → RA. Set CC if flagged.
Branch displacement	IP ← IP(Abus)+IR.compl(Bbus) (add)	Sign-extended displacement from IR added to IP.

cycles = 3 (fetch) + 2 × (number of [ ] indirection levels) + 1 (execute)

Instruction	Levels	Cycles
ADD RA RB	0	3+0+1 = 4
ADD RA [RB]	1	3+2+1 = 6
LOAD RA [[RB]]	2	3+4+1 = 8
STOR RA [RB]	1 (write)	3+1+1 = 5

4 · Cycle-count formula (sanity check)

If your cycle count does not match this, you missed or doubled a step. Recount.

A · ADD RA RB (0 levels → 4 cycles)

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: RA, CC ← RA(Abus) + RB(Bbus) (add) ; execute + flags

B · ADD RA [RB] (1 level → 6 cycles)

C · LOAD RA [[RB]] (2 levels → 8 cycles)

D · STOR RA [RB] (write → 5 cycles)

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: ΣA, ΣW ← RB(Bbus), RA(Abus) ; address = RB, data = RA 4: RAM[ΣA] ← ΣW ; write. no CC, no Cbus

E · BRS Ri disp (real 2026 Q4a, 10 pts)

Spec: store IP at RAM[ra−1], set Ri=ra−1, then IP += disp. Uses RAB = register on Bbus.

6 · Point-losers checklist (the stuff graders deduct for)

❌ Skipping the 3-cycle fetch.
❌ Two output-enables on the same bus in one cycle (bus contention) — only ONE driver per bus per cycle.
❌ Forgetting to set CC on ALU/LOAD instructions that require flags.
❌ Not naming the bus or ALU op on a cycle (write them even when "obvious").
❌ Using register names/buses that don't match the figure the exam gives you — copy theirs exactly.
❌ Wrong cycle count — always cross-check with the formula in §4.

7 · Full-marks ritual (do this on every Q4)

Write the 3 fetch cycles first, from memory.
Count the [ ] levels → predict the cycle count with the §4 formula.
Add 2 cycles per level using the read/write atom.
Add the execute cycle; set CC if needed.
Re-read each cycle: one driver per bus? ALU op named? bus named?
Final cycle number + 1 = your predicted count. Match? Done.

7 · Full-marks ritual (do this on every Q4)

Drill it now in the RTL Lab →

2IC30 · resource

RTL crashcourse

The fixed recipe that produces a full-marks Q4 answer.

Registers

IP instruction pointer · R0–R3 general · CC flags (visible)
IR instruction reg · ΣA RAM address · ΣR RAM read · ΣW RAM write (internal)

Three buses

Abus → ALU input A (IP, RA, ΣA)
Bbus → ALU input B (IP, IR, ΣR, RB via RAB)
Cbus → ALU result back to a register

0 · The machine you write for

ALU ops you name each cycle: incA (A+1), decA (A−1), loadA/loadB (pass through), add, sub, and, or, xor.

1 · ALWAYS start with the 3-cycle fetch

Memorise this verbatim. Every instruction begins with it. Writing it wins free points and never changes:

2 · The universal recipe

Write the 3 fetch cycles (cycles 0–2).
Fetch each operand — one dereference per [ ] level (see atoms below).
Execute — do the ALU op, write the result, set CC if the instruction sets flags.
Annotate every cycle: which bus carries each value + which ALU op (or "none").
Number cycles from 0.

3 · The atoms (reusable building blocks)

Every Q4 answer is these glued together. Learn the 5 atoms:

Atom	RTL	Notes
Read memory	ΣA ← addr · ΣR ← RAM[ΣA]	2 cycles. addr can be RB, IP, ΣR…
Write memory	ΣA, ΣW ← addr, data · RAM[ΣA] ← ΣW	load address + data, then store. No Cbus (it is a write).
Dereference [x]	ΣA ← x ; ΣR ← RAM[ΣA]	One per bracket level. [[x]] = do it twice.
ALU on two regs	RA, CC ← RA(Abus) op RB(Bbus)	1 cycle. Result on Cbus → RA. Set CC if flagged.
Branch displacement	IP ← IP(Abus)+IR.compl(Bbus) (add)	Sign-extended displacement from IR added to IP.

cycles = 3 (fetch) + 2 × (number of [ ] indirection levels) + 1 (execute)

Instruction	Levels	Cycles
ADD RA RB	0	3+0+1 = 4
ADD RA [RB]	1	3+2+1 = 6
LOAD RA [[RB]]	2	3+4+1 = 8
STOR RA [RB]	1 (write)	3+1+1 = 5

4 · Cycle-count formula (sanity check)

If your cycle count does not match this, you missed or doubled a step. Recount.

A · ADD RA RB (0 levels → 4 cycles)

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: RA, CC ← RA(Abus) + RB(Bbus) (add) ; execute + flags

B · ADD RA [RB] (1 level → 6 cycles)

C · LOAD RA [[RB]] (2 levels → 8 cycles)

D · STOR RA [RB] (write → 5 cycles)

0: ΣA, IP ← IP(Bbus), IP(Abus)+1 (incA) 1: ΣR ← RAM[ΣA] 2: IR ← ΣR(Bbus) (loadB) 3: ΣA, ΣW ← RB(Bbus), RA(Abus) ; address = RB, data = RA 4: RAM[ΣA] ← ΣW ; write. no CC, no Cbus

E · BRS Ri disp (real 2026 Q4a, 10 pts)

Spec: store IP at RAM[ra−1], set Ri=ra−1, then IP += disp. Uses RAB = register on Bbus.

6 · Point-losers checklist (the stuff graders deduct for)

❌ Skipping the 3-cycle fetch.
❌ Two output-enables on the same bus in one cycle (bus contention) — only ONE driver per bus per cycle.
❌ Forgetting to set CC on ALU/LOAD instructions that require flags.
❌ Not naming the bus or ALU op on a cycle (write them even when "obvious").
❌ Using register names/buses that don't match the figure the exam gives you — copy theirs exactly.
❌ Wrong cycle count — always cross-check with the formula in §4.

7 · Full-marks ritual (do this on every Q4)

Write the 3 fetch cycles first, from memory.
Count the [ ] levels → predict the cycle count with the §4 formula.
Add 2 cycles per level using the read/write atom.
Add the execute cycle; set CC if needed.
Re-read each cycle: one driver per bus? ALU op named? bus named?
Final cycle number + 1 = your predicted count. Match? Done.

7 · Full-marks ritual (do this on every Q4)

Drill it now in the RTL Lab →