2IC30 · assessment
Q4 RTL lab
Step the Conductor's micro-operations, then rebuild them from memory.
Register transfer micro-code
Step through the Conductor's micro-operations cycle by cycle. Every instruction shares the same three-cycle fetch; the execute phase varies by operand type.
Press Next to start
- 0fetch
ΣA, IP ← IP, IP+1
ΣA ← IP via Bbus (becomes the RAM address). IP via Abus, +1 (incA) → IP via Cbus. Both happen in one clock.
- 1fetch
ΣR ← RAM[ΣA]
Memory read: instruction word at address ΣA is loaded into ΣR.
- 2fetch
IR ← ΣR
ΣR placed on Bbus → IR. Conductor now holds the full instruction and can decode it.
- 3execute
RA, CC ← RA+RB, ALU.cc
RA on Abus, RB on Bbus → ALU adds → result via Cbus → RA. Condition codes (N,Z,C,V) updated.
Cycle-count quick reference
| Instruction type | No prefetch | With prefetch | Formula |
|---|---|---|---|
| ALU RA, RB (reg–reg) | 4 | 1 | 3 fetch + 1 exec |
| ALU RA, [RB] (indirect) | 6 | 3 | 3 + 2 operand + 1 exec |
| LOAD RA, [RB] | 6 | 3 | 3 + 2 read + 1 load |
| STOR RA, [RB] | 5 | 2 | 3 + 1 addr + 1 write |
| BEQ / BNE taken | 4 | 4 | 3 + 1 IP update (wastes prefetch) |
| BEQ / BNE not-taken | 3 | 1 | 3 fetch only |
| LOAD RA, [[RB]] (double) | 8 | 5 | 3 + 4 deref + 1 load |
RTL rules (exam essentials)
- Every instruction starts with three fetch cycles — never skip them.
- Only one output-enable is active per bus per cycle.
- Number every cycle starting from 0, and annotate the bus and ALU op.
- Set the condition codes where the instruction demands it (ALU ops and LOAD, not STOR).
- Use the exact register names from the datapath figure in the exam.