2IC30 · resource
Formula sheet
M2 Numbers
- Value in base b: ⟨a_{n-1}…a_0⟩_b = Σ a_i·b^i
- 2's-complement value: −a_{n-1}·2^{n-1} + Σ_{i<n-1} a_i·2^i
- 2's-complement range (n bits): −2^{n-1} … 2^{n-1}−1
- Negate (2's-comp): invert bits, then +1
- Horner: a_n y^n+…+a_0 = (((a_n)y + a_{n-1})y + …)+a_0 (n mults)
- Half adder: s=a⊕b, c=a∧b
- Full adder: s=a⊕b⊕c_in, c_out=(a∧b)∨(c_in∧(a⊕b))
- Overflow: V = carry_{n} ⊕ carry_{n-1} (signed)
M1 Logic
- De Morgan: ¬(x∨y)=¬x∧¬y ; ¬(x∧y)=¬x∨¬y
- Distributivity: x∧(y∨z)=(x∧y)∨(x∧z) ; x∨(y∧z)=(x∨y)∧(x∨z)
- Absorption: x∨(x∧y)=x ; x∧(x∨y)=x
- Complement-absorption: x∨(¬x∧y)=x∨y
- 2-input MUX: f = a0∧¬s ∨ a1∧s
- n inputs → 2^n truth-table rows → 2^{(2^n)} possible functions
- K-map group of 2^k cells removes k variables
M3 Timing
- Clock period: T ≥ t_pd,comb + t_pd,FF + t_su
- Max frequency: f_max ≤ 1/T
- Always: 0 < t_su + t_dh ; 0 ≤ t_oh ≤ t_pd
- Cascade FFs: t_dh ≤ t_oh
M5 Datapath
- Fetch: ΣA,IP ← IP(Bbus), IP(Abus)+1 (incA) ; ΣR ← RAM[ΣA] ; IR ← ΣR(Bbus) (loadB)
- Cycle count ≈ 3 (fetch) + 2×(indirect levels) + 1 (execute)
- Prefetch: ADD 4→1, XOR[addr] 6→3, STOR 5→2, BEQ taken 4→4 / not-taken 3→1
M6 Comparisons
- Unsigned: α β ⇔ C=0∧Z=0
- Signed: α β ⇔ N=V∧Z=0
- ARM shift: LSL #n = ×2^n ; LSR/ASR #n = ÷2^n
- Push = [--SP] ; Pull = [SP++]