2IC30Computer Systems

2IC30 · resource

Revision summaries

Digital Logic Foundations

  • 6 gate truth tables cold
  • De Morgan + distribute/absorb
  • minterm(1-rows)→DNF, maxterm(0-rows)→CNF
  • K-map: Gray axes, group 2^N×2^M, use don't-cares, cross-check duals
  • NAND & NOR each complete; {AND,OR} not; AND-OR=NAND-NAND

Number Systems & Arithmetic

  • decimal→base: divide, read remainders bottom-up; 4 bits=hex digit
  • 2's-comp: invert+1; MSB weight negative; range −2^{n-1}..2^{n-1}−1
  • sign-extend with the sign bit
  • overflow: same signs in, different sign out / carry_n≠carry_{n-1}
  • flags C,Z,N,V; half/full adder; ripple slow→look-ahead

Sequential Logic & Memory

  • SR latch forbidden S=R=1
  • latch transparent vs FF edge-triggered
  • setup before / hold after edge; f_max=1/(t_comb+t_FF+t_su)
  • registers: one OE per bus; 3-state Z; decoder+3-state=MUX

Finite State Machines

  • Moore=state-only output, Mealy=state+input
  • equivalent states (same out + same successors) merge
  • encodings: binary/Gray/one-hot
  • 7-step design flow; Karnaugh for next-state
  • sync safe vs async fast/fragile

Processor Architecture

  • visible IP,R0–R3,CC vs hidden IR,ΣA/W/R; 3 buses
  • fetch is 3 cycles; +2 per indirect; execute +1
  • direct vs indirect; STOR dest must be memory
  • RTL: name source, dest, bus, ALU op per cycle
  • prefetch savings; taken branch wastes prefetch; polling vs interrupts

Assembly & Programming

  • push [--SP], pull [SP++], stack grows down, balance before RTS
  • return address on stack → recursion; RTI restores flags
  • ARM: R13 SP/R14 LR/R15 PC; conditional exec + S; barrel shifter
  • large immediate via LDR =; BL/MOV PC,LR; SWI → supervisor
  • calling convention: reserve result, push args, adjust offsets after SUB SP locals

Compilers & System Architecture

  • interpreter vs compiler; parse→tree→templates
  • if/while/assign code templates; result left on stack
  • intermediate languages (LLVM/bytecode); optimisations
  • address vs data bus; SRAM vs DRAM; sync vs async bus
  • caches (why: speed gap), coherency, out-of-order + barriers, atomic primitives

Operating Systems & Memory Management

  • OS roles; context switch save→swap SP→restore→RTI
  • non-atomic x:=x+1 → semaphores/mutex
  • paging: page table + MMU; bits present/dirty/writeable/exec/protection
  • page fault: swap + retry instruction
  • FIFO/LRU both fail on big cyclic data; segmentation vs paging fragmentation