2IC30 · Topic 03
Sequential Logic & Memory
Adding memory: latches, flip-flops, timing, registers, buses and RAM.
Latches & flip-flops
Combinational circuits forget instantly. To remember a bit we need feedback. The building blocks are latches and flip-flops.
Ladder of storage elements: SR latch (cross-coupled NOR or NAND): Set makes Q=1, Reset makes Q=0, 0/0 holds. The forbidden input (both active) causes trouble. Gated SR latch : an enable E gates S,R so glitches are ignored while E=0. Still risks metastability if S=R=1 while E=1. D-latch (transparent latch) : derives S,R from one input D so S≠R always. While E=1 the output follows D (transparent); while E=0 it holds. Edge-triggered D flip-flop (e.g. 7474): copies D to Q only on the rising clock edge C↑. D need only be stable in a short window around the edge. JK flip-flop : toggles when both inputs are 1. T flip-flop : toggles when T=1.
Metastability : if S,R (or D near the clock edge) violate timing, the latch can hover between 0 and 1 unpredictably. Glitches are short unintended pulses from unequal gate delays; a gated latch makes them harmless. An edge detector (a fast gate plus a slow inverter) turns the level enable into a brief pulse — that is how an edge-triggered FF is made. The symbol distinction: a small triangle = edge-triggered; a bubble on the clock = falling-edge.
Every register, counter and pipeline stage is flip-flops. Metastability is a real hazard when sampling asynchronous inputs (buttons, other clock domains) — synchroniser FFs mitigate it.
Latches & flip-flops worked examples
1 questions
Common mistakes
- Confusing a level-sensitive latch (transparent while enabled) with an edge-triggered flip-flop (samples only at the edge).
- Forgetting the SR latch's forbidden state.
- Thinking the clock 'powers' the FF rather than timing the capture.
Exam tips
- Q3 circuits ask you to implement FSM state with clocked D flip-flops — treat them as standard components.
- Be able to explain glitch and metastability in one sentence each.
Memory aids
- Latch = transparent while enabled; flip-flop = snapshot at the edge.
- D-FF: 'D in now, Q out at the next tick'.
Latches & flip-flops practice
2 questions
Flip-flop timing: setup, hold, propagation
A flip-flop captures D at the clock edge, but only if D is steady around that edge. The timing parameters quantify 'around'.
t su setup time : D must be stable this long before C↑. t dh hold time : D must stay stable this long after C↑. t oh output-hold time : Q keeps its old value at least this long after C↑. t pd propagation delay : Q has its new value at most this long after C↑.
Always 0 < t su +t dh (a non-zero aperture), and 0 ≤ t oh ≤ t pd . Flip-flops can be safely cascaded iff t dh ≤ t oh (the new stage still sees the old value long enough). For a synchronous machine the maximum clock frequency is f max ≤ 1/T where T ≥ t pd(FF) + t pd(comb) + t su . If that bound holds, combinational glitches die out before the next edge and are harmless.
Static timing analysis on these exact inequalities determines a chip's clock speed; violating setup/hold causes intermittent, maddening hardware bugs.
Flip-flop timing: setup, hold, propagation worked examples
1 questions
Common mistakes
- Swapping setup (before edge) and hold (after edge).
- Forgetting the combinational delay in the clock-period formula.
- Ignoring the cascading condition t_dh ≤ t_oh.
Exam tips
- The f_max = 1/(t_pdc + t_pdf + t_su) relation is examinable — memorise the three terms.
- Glitches are 'harmless if they settle before the next clock edge'.
Memory aids
- S etup = S tart early (before edge); H old = H ang on (after edge).
- Clock period = FF delay + logic delay + setup.
Flip-flop timing: setup, hold, propagation practice
2 questions
Registers, register files & buses
A register is a row of n flip-flops sharing one clock and one enable, storing an n-bit word.
An enable (E) lets a register ignore clock edges until you actually want to load it. Several registers share an input bus and output bus ; only one drives the output bus at a time. Selecting which register reads/writes is done with enables plus multiplexers or 3-state outputs. A processor register file (REGS) typically supports 2 reads and 1 write simultaneously, with small address fields (ra, rb) selecting registers.
Sharing a bus among many registers via ordinary multiplexers costs an n-input MUX per bit; using 3-state outputs is cheaper and extensible — each register's output enable (OE) connects it to the shared wire only when selected. A decoder drives the OE lines so that exactly one is active. This bus discipline (at most one driver) is the same one used throughout the CPU datapath.
The register file is the fastest memory in a CPU; its read/write port count limits how many operands an instruction can touch per cycle.
Registers, register files & buses worked examples
1 questions
Common mistakes
- Enabling two bus drivers at once (short circuit / contention).
- Confusing the load-enable (input) with the output-enable.
- Thinking a register reloads every clock — the enable controls that.
Exam tips
- Datapath questions assume registers with IE (input enable) and OE (output enable) signals — name them in RTL.
- Only one OE may be 1 per bus per cycle.
Memory aids
- Register = byte-wide flip-flop bank with one clock + one enable.
- Bus rule: many listeners, ONE talker.
Registers, register files & buses practice
2 questions
3-state outputs, decoders & RAM
A 3-state buffer can output 0, 1, or 'Z' (disconnected/high-impedance). This lets many devices share one wire.
n→2ⁿ decoder : turns an n-bit address into 2ⁿ one-hot select lines (with an enable). A 2→4 decoder activates exactly one of d0..d3. RAM = an array of memory cells (flip-flops/latches with 3-state outputs) addressed by a decoder. A read-address decoder enables one cell onto the data-out bus; a write-address decoder steers data-in into one cell. The simple CPU's RAM is 512×16 (512 words of 16 bits).
Placing the 3-state buffer behind a latch's feedback means the cell can change state even while its output is disabled. Static RAM stores each bit in a latch (fast, simple wiring). Dynamic RAM stores each bit as charge on a capacitor — denser but needs periodic refresh and split row/column addressing (RAS/CAS); a DRAM controller (DDR2/3/4) hides this. ROM/flash connect like SRAM.
Address decoding is how the CPU maps an address to a physical memory location; memory-mapped I/O reuses the same decoders for devices.
3-state outputs, decoders & RAM worked examples
1 questions
Common mistakes
- Forgetting the decoder's enable input.
- Letting two RAM cells drive data-out at once.
- Confusing high-impedance Z with logic 0.
Exam tips
- Know the 2→4 decoder truth table and that a decoder + 3-state buffers = a MUX.
- RAM size notation R×W means R words of W bits.
Memory aids
- 3-state: 0, 1, or 'unplugged' (Z).
- Decoder = address → one-hot.
3-state outputs, decoders & RAM practice
2 questions